A Simple Denotational Semantics, Proof Theory and a Validation Condition Generator for Unit-Delay VHDL

A denotational semantics and a Hoare programming logic for a subset of the standard hardware description language vhdl are set out here. Both define the behaviour of synchronously clocked vhdl simulators in declarative and compositional style. The logic is proved complete with respect to the denotational semantics and a natural implementation of the logic in prolog as a validation condition generator for vhdl is also described. The subset of the language referred to above essentially consists of elaborated vhdl excluding only delta-delayed signal assignments and zero waits. However, for brevity, only one of the two forms of vhdl signal assignment is treated here. Moreover, for simplicity, signal resolution functions and local state are assumed to have been encoded away via expressions and signals.